A reproducing apparatus, such as an optical disc apparatus, a HDD (Hard Disk Drive), a digital video cassette or a data streamer, generates a clock from a reproduced signal acquired by reading a recording medium, and processes the reproduced signal using the generated clock, to reproduce data recorded on the recording medium.
FIG. 1 is a diagram showing a conventional configuration of a reproducing apparatus for recording media.
An equalizer 11 shapes a reproduced signal from a recording medium, and the reproduced signal is supplied to an A/D converter (Analog/Digital converter) 12.
The A/D converter 12 converts the reproduced signal, which is an analog signal supplied from the equalizer 11 into digital signals on the basis of reproduced clocks to be supplied from a clock generation section 13, and supplies the digital signals generated after the conversion, to the clock generation section 13 and an equalizer 14.
The clock generation section 13 includes a phase error detecting section 21 and a VCO (Voltage Controlled Oscillator) 22, and generates reproduced clocks using a PLL (Phase Locked Loop) system. The reproduced clocks are supplied to the A/D converter 12, the clock generation section 13, the equalizer 14 and a data detecting section 15.
A phase error integrating section 21 detects a phase error between a reproduced clock and the corresponding digital signal outputted from the A/D converter 12, and supplies a signal corresponding to the phase error, to the VCO 22.
The VCO 22 outputs a reproduced clock having such a frequency as to reduce the phase error, on the basis of the signal from the phase error detecting section 21. The reproduced clock is supplied further to the phase error detecting section 21.
The equalizer 14 shapes the digital signal on the basis of the reproduced clock, and supplies the shaped digital signal to the data detecting section 15.
The data detecting section 15 corrects the digital signal error by Viterbi decoding, and outputs the error-corrected digital signal as detected data.
When the recording medium has a defect, there occurs a deviation, i.e., a so-called bit slip, between a clock generated and data reproduced, from an input signal. When the bit slip has occurred, the error propagates to the subsequent data, leaving the error uncorrectable.
In order to avoid such a situation, specific patterns called synchronization patterns are arranged at predetermined intervals in the recording medium, whereby to prevent propagation of the error caused by the bit slip using the synchronization patterns.
There has been proposed a synchronization circuit (e.g., see Patent Document 1), in which: a synchronization pattern is detected from a digital signal; clock pulses are counted; a predicted synchronization pattern position is set on the basis of a count value; a predicted synchronization pattern range is set on the basis of the count value; a count value is held; a sync signal is outputted by referring to the detected synchronization pattern, the count value, the predicted synchronization pattern position, the set synchronization pattern range and the count value held, and the counter is reset by this sync signal. In this synchronization circuit, in a case where a synchronization pattern has been detected within the set predicted range, a sync signal is outputted at a timing at which the synchronization pattern has been detected, whereas in a case where no synchronization pattern has been detected within the set predicted range, a sync signal is outputted at the set timing. Moreover, in a case where a synchronization pattern has been detected beyond the set predicted range, a count value in the counter is compared with a count value held, and if both counts coincide, a sync signal is outputted at that timing, whereas if both count values do not coincide, the count in the counter is held.
Furthermore, there has been a synchronization circuit in which a phase deviation in a reproduced clock generated from a reproduced signal is detected, and any loss or gain in the reproduced signal is outputted as a bit slip detection signal, on the basis of this phase deviation, whereby to prevent propagation of an error caused by a bit slip (see Patent Document 2).
[Patent Document 1]
Japanese Patent Application Publication No. 8-212705
[Patent Document 2]
Japanese Patent Application Publication No. 10-255409
However, amidst growing incidences of signal defects due to dust and blemishes as the recording densities in recording media increase, prevention of propagation of burst errors merely with synchronization patterns is not enough to guarantee stable reading of data recorded on recording media.
Moreover, there may actually be cases where no synchronization pattern is detected throughout phase locking in the PLL after a bit slip has occurred due to a signal defect, and thus, despite the fact that the reproduced signal itself has recovered, the burst error propagates further to a next synchronization pattern, thus elevating the error rate.